Manager/Senior Engineer – MS/RF (San Jose)

• Responsibilities

1. A Strong technical leader

2. Build and lead a full scope engineering team that comprises circuit designers, digital designers, layout engineers, application engineers, software and firmware engineers, and testing/characterization engineers.

• Requirements

  1. Minimum master degree in Electronics Engineering or related field. Preferably with a Ph.D.

  2. Minimum 15 years of experience in mixed-signal, high-speed interface or CMOS RF design and design management.

  3. Ideal candidates may be from major IC industry's internal design or development group and are currently holding titles such as Senior Managers, Directors or technical Fellows. Should be a very strong technical leader, who can give technical guidance on mixed-signal and/or high-speed link designs.

  4. Must have experience in building and/or leading a full scope engineering team that comprises circuit designers, digital designers, layout engineers, application engineers, software and firmware engineers, and testing/characterization engineers.

  5. Those with business acumen would be advantageous, especially with experience or capability in working with large fabless customers on engineering collaboration projects as well as those with strong operation management experience including managing a cost center.

  6. Deep understanding and be abreast of the market and industry knowledge on high-end consumer and/or communication/mobile sectors.

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Manager – Embedded DRAM

• Responsibilities

 The role is responsible for Nanometer high density embedded DRAM design and/or customer engagement.

• Requirements

  1. Minimum bachelor degree in Electronics Engineering or Physics field.

  2. Minimum 8 yrs of experiences in DRAM or embedded DRAM design.

  3. Strong communication and project management skills.

  4. Fluent in English.

  5. Work location in Hsinchu, Taiwan or San Jose, USA.

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Manager – SRAM

• Responsibilities 

The role is responsible for Nanometer high density SRAM and embedded SRAM compiler design.

• Requirements
  

  1. Minimum bachelor degree in Electronics Engineering or Physics field.

  2. Minimum 8 yrs of experiences in DRAM or embedded DRAM design.

  3. Strong communication and project management skills.

  4. Fluent in English.

  5. Work location in Hsinchu, Taiwan or San Jose, USA.

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Manager/Senior Engineer – Layout (San Jose)

• Responsibilities

 Perform layout design for mixed-signal and/or high-speed circuits

• Requirements

  1. Minimum 3 years experience in mixed-signal or high-speed circuit design

  2. Minimum 1 year experience in advanced technology (90nm and below) circuit layout

  3. Strong team work orientation.

  4. Good communication skills

  5. Work location in San Jose, USA.

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Manager/Senior Engineer – High Speed Design

• Responsibilities

 1. Participate in the high-speed IP development work

2. Customize high-speed IPs

3. High-speed IPs design porting service

• Requirements
  

  1. Minimum bachelor degree in Electronics Engineering or Physics field.

  2. Minimum 3 years experience in mixed-signal or high-speed circuit design

  3. Strong team work orientation.

  4. Strong communication skills

  5. Work location in Hsinchu, Taiwan or San Jose, USA.

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Manager – Chip/IP Design Service Project Management

The role is responsible for design service promotion, customer project engagement, business/schedule/resource/issue management.

To meet goals of business and customer satisfaction.

• Requirements
  

  1. Minimum master degree in Electronics Engineering or related field.

  2. Minimum 6 years of working experiences in one or several of the following:

  - IC front-end design experience

  - IC physical design experience

  - IC design flow development (CAD)

  3. Familiar to ASIC design service business and operation

  4. Experience in leading project and own overall project responsibility

  5. Experience in Deep Sub-micron design (0.13u and below) is a plus

  6. Strong communication and project management skills

  7. Fluent in English.

  8. Work location in Hsinchu, Taiwan.

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Manager – PDK (San Jose)

• Responsibilities 

1. To provide customer first line support for TSMC PDK/DRC/LVS/RCX

2. Customize TSMC PDK/DRC/LVS/RCX to meet customers' special requests

3. Enhance current tech files structure, documents and interface.

• Requirements

  1. EE or IT Graduated or above

  2. 8+ years experience in MM/RF design or CAD experience in developing PDK/DRC/LVS/RCX

  3. Hand-on knowledge in Cadence PDK, Calibre, Hercules, Assura run and debugging

  4. Good communication skill with customers, vendors

  5. Familiar in scripting language like Perl

  6. Capable to work independently and work with other groups to provide solution

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Manager – CAE (San Jose)

• Responsibilities

 1. Serve as Sr. staff for special assignment (i.e. strategy, new initiatives, planning).

2. Sever as Head of CAE organization to:

•  Re-build CAE operations,
• Oversee Lib/IP release and communications,
• Provide technical support to FAE and customers,
• Ensure technical documentation and sales collateral quality and coordination.

• Requirements

  1. Minimum master degree in Electronics Engineering or Computer Science.

  2. Minimum 8 years experience in IC/IP design and EDA tools.

  3. Strong communication and project management skills

  4. Fluent in English.

  5. Work location in Hsinchu, Taiwan.

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